rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg466/adg467 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 triple and octal channel protectors functional block diagrams adg466 adg467 v d1 v d2 v d3 v s1 v s2 v s3 v d1 v d2 v d3 v d8 v s1 v s2 v s3 v s8 v dd v ss v dd v ss v in v dd v dd v in v out output clamped @ v dd ?1.5v v out general description the adg466 and adg467 are triple and octal channel pro- tectors, respectively. the channel protector is placed in series with the signal path. the channel protector will protect sensitive components from voltage transience in the signal path whether the power supplies are present or not. because the channel protection works whether the supplies are present or not, the channel protectors are ideal for use in applications where correct power sequencing cant always be guaranteed (e.g., hot-insertion rack systems) to protect analog inputs. this is discussed further, and some example circuits are given in the applications section of this data sheet. each channel protector has an independent operation and consists of an n-channel mosfet, a p-channel mosfet and an n-channel mosfet, connected in series. the channel protector behaves just like a series resistor during normal operation, i.e., (v ss + 2 v) < v in < (v dd C 1.5 v). when a channels analog input exceeds the power supplies (including v dd and v ss = 0 v), one of the mosfets will switch off, clamping the output to either v ss + 2 v or v dd C 1.5 v. circuitry and signal source protection is provided in the event of an overvoltage or power loss. the channel protectors can withstand overvoltage inputs from C40 v to +40 v. see the circuit information section of this data sheet. the adg466 and adg467 can operate off both bipolar and unipolar supplies. the channels are normally on when power is connected and open circuit when power is disconnected. with power supplies of 15 v, the on-resistance of the adg466 and features fault and overvoltage protection up to 6 40 v signal paths open circuit with power off signal path resistance of r on with power on 44 v supply maximum ratings low on resistance adg466/adg467 60 v typ 1 na max path current leakage @ +25 8 c low r on match (5 v max) low power dissipation 0.8 m w typ latch-up proof construction applications ate equipment sensitive measurement equipment hot-insertion rack systems adg467 is 50 w typ with a leakage current of 1 na max. when power is disconnected, the input leakage current is approximately 5 na typ. the adg466 is available in 8-lead dip, soic and m soic packages. the adg467 is available in an 18-lead soic package and a 20-lead ssop package. product highlights 1. fault protection. the adg466 and adg467 can withstand continuous voltage inputs from C40 v to +40 v. when a fault occurs due to the power supplies being turned off or due to an overvolt- age being applied to the adg466 and adg467, the output is clamped. when power is turned off, current is limited to the microampere level. 2. low power dissipation. 3. low r on . adg466/adg467 60 w typ. 4. trench isolation latch-up proof construction. a dielectric trench separates the p- and n-channel mosfets thereby preventing latch-up. obsolete
C2C rev. 0 adg466/adg467Cspecifications dual supply 1 adg466 adg467 parameter +25 8 cb 1 +25 8 cb 1 units test conditions/comments fault protected channel fault-free analog signal range 2 v ss + 1.2 v ss + 1.2 v min output open circuit v dd C 0.8 v dd C 0.8 v max r on 60 75 62 80 w typ C10 v v s +10 v, i s = 1 ma 80 95 w max d r on 34 6 w max C5 v v s +5 v r on match 4 6 5 6 w max v s = 10 v, i s = 1 ma leakage currents channel output leakage, i s(on) v s = v d = 10 v (without fault condition) 0.1 1 0.04 0.2 na typ 1 5 1 5 na max channel input leakage, i d(on) v s = 25 v (with fault condition) 0.2 0.4 0.2 0.4 na typ v d = open circuit 2 5 2 5 na max channel input leakage, i d(off) v dd = 0 v, v ss = 0 v (with power off and fault) 0.5 2 0.5 2 na typ v s = 35 v, 1 5 2 10 na max v d = open circuit channel input leakage, i d(off) v dd = 0 v, v ss = 0 v (with power off and output s/c) 0.005 0.1 0.006 0.16 m a typ v s = 35 v, v d = 0 v 0.015 0.5 0.015 0.5 m a max power requirements i dd 0.05 0.05 m a typ 0.5 8 0.5 8 m a max i ss 0.05 0.05 m a typ 0.5 8 0.5 8 m a max v dd /v ss 0 0 0 0 v min 20 20 20 20 v max notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +15 v, v ss = C15 v, gnd = 0 v, unless otherwise noted) obsolete
adg466/adg467 C3C rev. 0 absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 v v s , v d , analog input overvoltage with power on 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss C 20 v to v dd + 20 v v s , v d , analog input overvoltage with power off 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C35 v to +35 v continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 125 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c soic package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 160 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c m soic package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 160 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 130 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at s or d will be clamped by the channel protector, see circuit information section of the data sheet. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg466/adg467 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations 8-lead dip, soic 18-lead and m soic soic 1 2 3 4 8 7 6 5 top view (not to scale) adg466 v d1 v s3 v s2 v s1 v dd v d2 v d3 v ss 14 13 12 11 17 16 15 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) adg467 v d1 v s3 v s2 v s1 v dd v d2 v d3 v d4 v s6 v s5 v s4 v d5 v d6 v d7 v d8 v ss v s8 v s7 20-lead ssop v d1 v s3 v s2 v s1 v dd v d2 v d3 v d4 v s6 v s5 v s4 v d5 v d6 v d7 v d8 v ss v s8 v s7 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) adg467 nc = no connect nc nc ordering guide model temperature range package description package option adg466bn C40 c to +85 c 8-lead plastic dip n-8 adg466br C40 c to +85 c 8-lead small outline package so-8 adg466brm C40 c to +85 c 8-lead micro small outline package rm-8 adg467br C40 c to +85 c 18-lead small outline package r-18 adg467brs C40 c to +85 c 20-lead shrink small outline package rs-20 obsolete
adg466/adg467Ctypical performance characteristics C4C rev. 0 v d ?volts r on ? w 80 75 30 ?0 10 ? 0 5 60 45 40 35 70 65 50 55 v dd , v ss = 6 5v v dd , v ss = 6 10v 6 16.5v v dd , v ss = 6 13.5v v dd , v ss = 6 15v adg466 figure 1. on resistance as a function of v dd and v d (input voltage) 70 65 25 ?0 10 ? 0 5 50 40 35 30 60 55 45 125 8 c 85 8 c 25 8 c ?0 8 c v d ?volts r on ? w v dd = +15v v ss = ?5v figure 2. on resistance as a function of temperature and v d (input voltage) 6 16.5v adg467 v d ?volts 105 95 45 -10 10 ? r on ? w 05 85 75 65 55 6 5v 6 15v 6 13.5v 6 10v figure 3. on resistance as a function of v dd and v d (input voltage) ch1 10v 500mv 5.00v ch2 5.00v m50.0ns ch1 0v ?v 15v 5v ?v to +15v step input channel protector output positive overvoltage r load = 100k w on input c load = 100pf v dd = +10v v ss = ?0v figure 4. positive overvoltage transience response ch2 500mv ch1 5.00v 5.00v m50.0ns ch1 negative overvoltage on input r load = 100k w c load = 100pf v dd = +10v v ss = ?0v channel protector output 5v to ?5v step input ?0v 5v 0v ?v ?5v figure 5. negative overvoltage transience response 1 ? 500mv 5.00v ch2 5.00v m100? ch1 2 ? output v clamp =4v v clamp =4.5v 10v to +10 v input r load =100k w v dd =+5v v ss =?v ch1 20v figure 6. overvoltage ramp obsolete
adg466/adg467 C5C rev. 0 circuit information figure 7 below shows a simplified schematic of a channel protector circuit. the circuit is made up of four mos transis- torstwo nmos and two pmos. one of the pmos devices does not lie directly in the signal path but is used to connect the source of the second pmos device to its backgate. this has the effect of lowering the threshold voltage and so increasing the input signal range of the channel for normal operation. the source and backgate of the nmos devices are connected for the same reason. during normal operation the channel protectors have a resistance of 60 w typ. the channel protectors are very low power devices, and even under fault conditions the supply current is limited to sub micro-ampere levels. all transistors are dielectrically isolated from each other using a trench isolation method. this makes it impossible to latch up the channel protectors. for an explanation, see trench isolation section. nmos pmos pmos nmos v dd v ss v ss v dd figure 7. the channel protector circuit overvoltage protection when a fault condition occurs on the input of a channel protector, the voltage on the input has exceeded some threshold voltage set by the supply rail voltages. the threshold voltages are related to the supply rails as follows. for a positive overvolt- age, the threshold voltage is given by v dd C v t where v tn is the threshold voltage of the nmos transistor (1.5 v typ). in the case of a negative overvoltage the threshold voltage is given by v ss C v tp where v tp is the threshold voltage of the pmos device (2 v typ). if the input voltage exceeds these threshold voltages, the output of the channel protector (no load) is clamped at these threshold voltages. however, the channel protector output will clamp at a voltage that is inside these thresholds if the output is loaded. for example with an output load of 1 k w , v dd = 15 v and a positive overvoltage. the output will clamp at v dd C v tn C d v = 15 v C 1.5 v C 0.6 v = 12.9 v where d v is due to i r voltage drop across the channels of the mos devices (see figure 9). as can be seen from figure 9, the current during fault condition is determined by the load on the output (i.e., v clamp /r l ). however, if the supplies are off, the fault current is limited to the nano-ampere level. figures 8, 10 and 11 show the operating conditions of the signal path transistors during various fault conditions. figure 8 shows how the channel protectors operate when a positive overvoltage is applied to the channel protector. nmos pmos nmos v dd (+15v) v ss (?5v) v dd (+15v) positive overvoltage (+20v) v dd ?v tn * (+13.5v) *v tn = nmos threshold voltage (+1.5v) non- saturated non- saturated saturated figure 8. positive overvoltage on the channel protector the first nmos transistor goes into a saturated mode of operation as the voltage on its drain exceeds the gate voltage (v dd ) C the threshold voltage (v tn ). this situation is shown in figure 9. the potential at the source of the nmos device is equal to v dd C v tn . the other mos devices are in a nonsaturated mode of operations. when a negative overvoltage is applied to the channel protector circuit, the pmos transistor enters a saturated mode of opera- tion as the drain voltage exceeds v ss C v tp . see figure 10 be- low. as in the case of the positive overvoltage, the other mos devices are nonsaturated. nmos pmos nmos v dd (+15v) v ss (?5v) v dd (+15v) negative overvoltage (?0v) v ss ?v tp * (?3v) *v tp = pmos threshold voltage (?v) negative overvoltage (?0v) non- saturated non- saturated saturated figure 10. negative overvoltage on the channel protector v s n + (v dd =15v) v d p n + n + (+20v) (+13.5v) overvoltage operation (saturated) v t = 1.5v (v g ?v t = 13.5v) v g effective space charge region n channel nmos pmos nonsaturated operation r l d v i out v clamp figure 9. positive overvoltages operation of the channel protector obsolete
adg466/adg467 C6C rev. 0 the channel protector is also functional when the supply rails are down (e.g., power failure) or momentarily unconnected (e.g., rack system). this is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see applications information). when v dd and v ss equal 0 v, all transistors are off and the current is limited to subnano-ampere levels (see figure 11). nmos pmos nmos v dd (0v) v ss (0v) v dd (0v) positive or negative overvoltage (0v) off off off figure 11. channel protector supplies equal to zero volts trench isolation the mos devices that make up the channel protector are isolated from each other by an oxide layer (trench) (see figure 12). when the nmos and pmos devices are not electrically isolated from each other, there exists the possibility of latch- up caused by parasitic junctions between cmos transistors. latch-up is caused when p-n junctions that are normally reverse biased become forward biased, causing large currents to flow, which can be destructive. cmos devices are normally isolated from each other by junction isolation . in junction isolation, the n and p wells of the cmos transistors form a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode becomes forward biased. a silicon-controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. with trench isolation, this diode is removed; the result is a latch-up proof circuit. v g v d p-channel p + p + v s n v g v d n-channel n + n + v s p t r e n c h t r e n c h t r e n c h buried oxide layer substrate (backgate) figure 12. trench isolation applications information overvoltage and power supply sequencing protection the adg466 and adg467 are ideal for use in applications where input overvoltage protection is required and correct power supply sequencing cannot always be guaranteed. the overvoltage protection ensures that the output voltage of the channel protector will not exceed the threshold voltages set by the supplies (see circuit information) when there is an overvoltage on the input. when the input voltage does not exceed these threshold voltages, the channel protector behaves like a series resistor (60 w typ). the resistance of the channel protector does vary slightly with operating conditions (see typical performance graphs). the power sequencing protection is afforded by the fact that when the supplies to the channel protector are not connected, the channel protector becomes a high resistance device. under this condition all transistors in the channel protector are off and the only currents that flow are leakage currents, which are at the m a level. v dd v ss +5v ?v edge connector adg466 adc control logic analog in ?.5v to +2.5v logic logic gnd figure 13. overvoltage and power supply sequencing protection figure 13 shows a typical application that requires overvoltage and power supply sequencing protection. the application shows a hot-insertion rack system. this involves plugging a circuit board or module into a live rack via an edge connector. in this type of application it is not possible to guarantee correct power supply sequencing. correct power supply sequencing means that the power supplies should be connected before any external signals. incorrect power sequencing can cause a cmos device to latch up. this is true of most cmos devices regardless of the functionality. rc networks are used on the supplies of the channel protector (figure 13) to ensure that the rest of the circuitry is powered up before the channel protectors. in this way, the outputs of the channel protectors are clamped well below v dd and v ss until the capacitors are charged. the diodes ensure that the supplies on the channel protector never exceed the supply rails of the board when it is being disconnected. again this ensures that signals on the inputs of the cmos devices never exceed the supplies. obsolete
adg466/adg467 C7C rev. 0 high voltage surge suppression the adg466 and adg467 are not intended for use in high voltage applications like surge suppression. the adg466 and adg467 have breakdown voltages of v ss C 20 v and v dd + 20 v on the inputs when the power supplies are con- nected. when the power supplies are disconnected, the break- down voltages on the input of the channel protector are 35 v. in applications where inputs are likely to be subject to overvolt- ages exceeding the breakdown voltages quoted for the channel protectors, transient voltage suppressors (tvss) should be used. these devices are commonly used to protect vulnerable circuits from electric overstress such as that caused by electrostatic discharge, inductive load switching and induced lightning. how- ever, tvss can have a substantial standby (leakage) current (300 m a typ) at the reverse standoff voltage. the reverse standoff voltage of a tvs is the normal peak operating voltage of the circu it. also tvs offer no protection against latch-up of sensitive cmos devices when the power supplies are off. the best solution is to use a channel protector in conjunction with a tvs to provide the best leakage current specification and circuit protection. adg466 v dd = +5v v ss = ?v adc tvss breakdown voltage = 20v figure 14. high voltage protection figure 14 shows an input protection scheme that uses both a tvs and channel protector. the tvs is selected with a reverse standoff voltage that is much greater than operating voltage of the circuit (tvss with higher breakdown voltages tend to have better standby leakage current specifications) but is inside the breakdown voltage of the channel protector. this circuit pro- tects the circuitry whether the power supplies are present or not. obsolete
adg466/adg467 C8C rev. 0 outline dimensions dimensions shown in inches and (mm). c2207C12C10/96 printed in u.s.a. 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 18-lead small outline ic (r-18) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 18 10 9 1 0.4625 (11.75) 0.4469 (11.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 8-lead small outline ic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 20-lead shrink small outline package (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 8-lead micro small outline ic (rm-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) obsolete
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